Integrated circuit memory devices typically include one or more arrays of memory cells that store data. The data is either read from or written to the memory cell using data communication connections. Some example memory devices include but are not limited to random access memories (RAM), dynamic random access memories (DRAM), Synchronous DRAM (SDRAM), static RAM (SRAM), and non-volatile memories such as FLASH.
During production of the memory devices, the individual memory cells need to be tested. Thus, data is written to the memory cells and then the data is read from the memory. As the density of the memory arrays increase, the time needed to fully test the memory array also increases.
One technique that can be used to decrease test time is data compression. That is, data read from multiple memory cells are compressed into a smaller number of data bits. Thus, less data communication connections (DQ's) are required for a given number of memory cells when implementing data compression. The data compression circuitry is included in the memory device and adds overhead to the data read and write paths. This overhead can decrease operating speeds during normal, non-test operations.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device having data compression circuitry while maintaining suitable operating speeds during normal, non-test operations